The present invention relates to a manufacturing method of a semiconductor device.
A survey done after the invention had been made reported to the inventors the existence of inventions described in The International Technology Roadmap for Semiconductors, pp. 5 to 6 (1999) (hereafter, it is referred to as related art 1), IEEE, pp. 118 to 123 (1998) (hereafter, it is referred to as related art 2), and Japanese patent Laid-Open No. 104313/1998 (hereafter, it is referred to as related art 3).
The related art 1 abstractedly describes that it will be needed to provide a current seneor, to divide a power supply or to control back bias because the determination of good items/detectives by the IDD quiescent test is expected to be difficult due to an increase in leakage current associated with the realization of high integration. The related art 2 describes the IDD quiescent test and the low voltage test. The related art 3 describes a semiconductor integrated circuit where the output of a random pattern generator is inputted from a latch to a combinational circuit and the exclusive OR of the output is tested. However, the idea such that the leakage current in a CMOS static type circuit is detected by circuit operations or that is applied to the semiconductor device fabrication, as similar to the invention described later, is seen in none of the related arts 1 to 3.
Because of the progress in semiconductor technologies, when an MOSFET is formed to have a low threshold voltage for the realization of down-scaling or speeding devices, or a circuit scale is increased to form many elements, an occupied ratio of the leakage current, which is referred to as a threshold leakage current flowing through a source-to-drain path of the MOSFET in the OFF state or tailing, is increased in a direct current IDD quiescent flowing between a power supply tenninal and an earthing terminal of the semiconductor device, as associated with that. Thus, the determination of good items/defectives by the IDD quiescent test becomes difficult as described above. Then, the inventors considered finding those closely related to circuit operation failures in the leakage current by utilizing the circuit operations, instead of measuring a current itself in the past.
The purpose of the invention is to provide a manufacturing method of a semiconductor device capable of obtaining highly reliable semiconductor devices with the realization of high integration and high speed intended and a testing method of a semiconductor device. The aforementioned and other purposes and novel features of the invention will be apparent from the description of the specification and the accompanying drawings.
A summary of a representative invention among the inventions disclosed in the application will be described briefly as follows. During processes after a desired circuit including a CMOS static type circuit is formed on a semiconductor substrate until product shipment, a first operation of feeding a predetermined input signal to the circuit and retrieving a first output signal corresponding to it and a second operation of giving an operating condition of increasing an ON resistance value of MOSFETs constituting the CMOS static type circuit and retrieving a second output signal corresponding to the condition are conducted, and a testing step of determining a failure by the first output signal varying from the second signal is provided.